1. Field of the Invention
The present invention relates to a method for fabricating a liquid crystal display (LCD) device having thin film transistors and, more particularly, to a method for fabricating an LCD capable of using an etch stopper without additionally using a mask.
2. Discussion of the Related Art
Display devices, in particular, flat panel display such as a liquid crystal display (LCD), include an active element such as a thin film transistor (TFT) in each pixel so as to be driven. This type of display device driving method is generally called an active matrix driving method.
In the active matrix driving method, the active element is disposed in each of pixels arranged in a matrix form and drives each pixel.
A method for fabricating the related art active matrix type LCD will now be described with reference to FIG. 1.
With reference to FIG. 1, the related art LCD uses TFTs 10 as active elements.
In the LCD, the N×M number of pixels are disposed horizontally and vertically on an array substrate (not shown), and each pixel includes gate lines 13 for receiving scan signals from an external driving circuit, data lines 21 for receiving image signals from an external driving circuit, and TFTs 10 formed at each crossing of the gate lines 13 and data lines 21.
Herein, the TFT 10 includes a gate electrode 13a connected with the gate line 13, a semiconductor layer pattern 17a formed on the gate electrode 13 and activated when a scan signal is applied to the gate line 13, and source and drain electrodes 21a and 21bformed on the semiconductor layer pattern 17a. 
A pixel electrode 25 is formed at a display region of the pixel and connected with the source and drain electrodes 21a and 21b. When the semiconductor layer pattern 17a is activated, the pixel electrode 25 receives an image signal through the source and drain electrodes 21a and 21b to operate liquid crystal (not shown).
The structure of the related art LCD will now be described with reference to FIG. 2.
FIG. 2 is a sectional view taken along line II-II of the related art LCD in FIG. 1
With reference to FIG. 2, a TFT (10 in FIG. 1) is formed on a first substrate 11 made of a transparent material such as glass.
The TFT 10 includes a gate electrode 13a formed on the first substrate 11, a gate insulation layer 15 formed on the entire surface of the first substrate 11 with the gate electrode 13a formed thereon, a semiconductor layer pattern 17a formed on the gate insulation layer 15; an etch stopper pattern 19a formed on a channel region of the semiconductor layer pattern 17a, source and drain electrodes 21a and 21b formed on the semiconductor layer at both sides of the etch stopper pattern 19a, and a passivation layer 23 formed on the entire surface of the first substrate 11.
A pixel electrode 25 is formed on the passivation layer 23 and connected with the drain electrode 21b of the TFT 10 through a contact hole (not shown) formed in the passivation layer 23.
On the second substrate 31 made of a transparent material such as glass, there are formed a black matrix 33 at the TFT formation region or an image non-display region such as between pixels in order to prevent light transmission to the image non-display region and a color filter layer 35 including red, green and blue to implement actual colors.
To finish fabrication of the LCD, a liquid crystal layer 41 is provided between the first and second substrates 11 and 31.
The related art LCD is fabricated through a complicated process such as a photolithography which mainly uses a mask. The method for fabricating the related art LCD will now be described with reference to FIGS. 3A to 3E.
FIGS. 3A to 3E are process sectional views showing a fabrication process of the general LCD.
First, as shown in FIG. 3A, a metal is provided on the first substrate 11 to form a metallic layer (not shown), on which a first photosensitive film (not shown) is coated and baked at a certain temperature.
Next, a first mask (not shown) is positioned above the first photosensitive film through a first masking process, light such as an ultraviolet ray is irradiated onto the first photosensitive film, and a developing process is performed thereon to form a first photosensitive film pattern (not shown).
Subsequently, in a state that the metallic layer (not shown) is blocked, the first photosensitive film pattern is etched to form the gate line 13 and the gate electrode 13a extending in a vertical direction from the gate line on the first substrate 11.
Next, after the first photosensitive film pattern is removed, the gate insulation layer 15, the semiconductor layer 17 and the etch stopper 19 are sequentially formed on the entire surface of the first substrate 11 including the gate electrode 13a. 
Subsequently, the second photosensitive film (not shown) is coated on the etch stopper 19, on which a second mask (not shown) is positioned, light such as ultraviolet ray is irradiated thereto, and then a developing process is performed to form a second photosensitive film pattern (not shown) through a second masking process. At this time the second photosensitive film pattern is formed only at the etch stopper 19 corresponding to a channel region of the semiconductor layer 17.
Next, as shown in FIG. 3B, when the etch stopper 19 positioned on the channel region is blocked by the second photosensitive film pattern (not shown), the etch stopper 19 is selectively etched to form an etch stopper pattern 19a. 
Then, as shown in FIG. 3C, after the second photosensitive film pattern is removed, an n+ a-Si:H layer (not shown) is deposited on the entire surface of the first substrate 11.
After a third photosensitive film (not shown) is coated on the n+ a-Si:H layer (not shown), a third mask is positioned at an upper position of the third photosensitive film, on which light such as an ultraviolet ray is irradiated thereto. Then, a developing process is performed to form a third photosensitive film pattern (not shown) through a third masking process.
Thereafter, in a state that a portion of the semiconductor layer 17 is blocked using the third photosensitive film pattern (not shown), the n+ a-Si:H layer and the semiconductor layer 17 are selectively etched to form an ohmic contact layer (not shown) and a semiconductor layer pattern 17a. 
Subsequently, as shown in FIG. 3C, after the third photosensitive film pattern is removed, a metallic conductive material layer 21 is deposited on the entire surface of the first substrate, on which a fourth photosensitive film (not shown) is then coated.
When a fourth mask (not shown) is positioned at an upper portion of the fourth photosensitive film, light such as an ultraviolet ray is irradiated thereto, and then, a developing process is performed to form a fourth photosensitive film pattern (not shown) through a fourth masking process.
In this case, the fourth photosensitive film pattern (not shown) exists only at a region corresponding to the source/drain electrode formation region.
The fourth photosensitive film pattern (not shown) does not exist on a metallic conductive material layer region positioned at the channel region.
Thereafter, as shown in FIG. 3D, the metallic conductive material layer is selectively etched by using the fourth photosensitive film pattern to form the source and drain electrodes 21a and 21b. 
At this time, the metallic conductive material layer positioned above the channel region is also removed, and in this case, because the etch stopper pattern 19a exists below the metallic conductive material layer, the channel cannot be damaged.
Subsequently, as shown in FIG. 3E, the fourth photosensitive film pattern (not shown) is removed, the passivation layer 23 is deposited by more than a certain thickness on the first substrate 11, on which a fifth photosensitive film (not shown) is coated.
And then, when a fifth mask (not shown) is positioned at an upper portion of the fifth photosensitive film, light such as an ultraviolet ray is irradiated thereto, and then, a developing process is performed to form a fifth photosensitive film pattern (not shown) through a fifth masking process.
Thereafter, the passivation layer 23 is selectively etched using the fifth photosensitive film pattern (not shown) to form a contact hole (not shown) exposing the drain electrode 21b. 
And then, after the fifth photosensitive film pattern is removed, a transparent conductive material such as ITO is deposited on the passivation layer 23 including the contact hole (not shown).
Subsequently, when a fifth mask (not shown) is positioned at an upper portion of the transparent conductive material layer, light such as ultraviolet ray is irradiated thereto, and then a developing process is performed to form a sixth photosensitive film pattern (not shown) through a sixth masking process.
Thereafter, the transparent conductive material layer is selectively etched using the sixth photosensitive film pattern to form the pixel electrode 25 electrically connected with the drain electrode 21b, and then, the sixth photosensitive film pattern is removed.
And then, as shown in FIG. 3E, the black matrix 33 and the color filter layer 35 are formed on the second substrate 31.
The first and second substrates 11 and 12 are attached with a certain gap therebetween, into which the liquid crystal layer 41 is formed to thus finish fabrication of the LCD.
As mentioned above, the related art method for fabricating the LCD has the following problems.
That is, in the existing 5-mask structure, because the channel region of the semiconductor layer is plasma-damaged during an etching process for forming the source and drain electrodes, deteriorating the TFT characteristics, and thus, the etch stopper is used.
In this respect, however, as the etch stopper is used, the masking process is additionally performed. As a result, the number of masking processes increases, the fabrication process is complicated, and the fabrication process cost increases.